![]() Fig. 1: Electronic combination lock circuit |
The clock pulse advances IC1's count by one, so O0 goes low and O1 goes high. Therefore press switch S7 next, as it's wired to output O1. The time required for capacitor C1 to charge to logic high level is the maximum time that can lapse between switches pressed. Otherwise, the counter will reset. When all switches have been pressed in the correct sequence (S2-S7-S3-S4-S5-S2-S2 as shown), output O7 (pin 10) of the counter goes high for about ten seconds. This output is fed to driver transistor T2 to drive the solenoid valve and open the lock.
![]() Fig. 2: Pin configurations of BC548 and BD139 |
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